ASIC Clocks Engineer - New College Grad 2023
Oski Technology
Santa Clara, California
Job Description
We are now hiring for an ASIC Design Engineer New College Grad on our Clocks team!
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today.
The GPU clocks group is looking for an exceptional ASIC engineer. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.
What you'll be doing:
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As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clock structures.
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You should be able to engage with multiple teams and design the GPU clock structure to satisfy all the architectural constraints.
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Your understanding of general verification principles will be valuable to verify the clocks design.
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Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to improve the productivity of the above teams.
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Collaborate with Software and product group to debug GPU clock silicon bugs in our new products.
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Understand and design clocking structures to overcome sub-micron design challenges.
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Identify improvements in the current design and propose and implement new ways to improve the efficiency in the GPU clocking design.
What we need to see:
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BS or MS (preferred) in EE or equivalent experience.
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Ability to thrive in a dynamically changing environment.
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Experience in RTL design (Verilog), verification and logic synthesis.
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Strong coding skills in Perl or other industry-standard scripting languages
You will also be eligible for equity and
benefits
.
